The invention relates to lock detector circuits in phase locked loop circuits.
Phase locked loop circuits have played important roles in electronic systems since the early 1930""s. A phase locked loop (PLL) is a feedback circuit which may comprise a phase detector or comparator, a loop filter, and a voltage controlled oscillator (VCO). The phase detector receives and compares either phase or frequency of an incoming reference signal with a sample of the feedback signal. The loop filter removes high frequency components of the phase difference between the two signals. The low frequency components of the difference in phase or frequency of the two signals drives the VCO to produce a new sample of the feedback signal which is better matched in frequency or phase with the reference signal. This process continues until both signals are in a locked condition. Therefore, the PLL can lock the phase or frequency of a reference signal into a fixed phase or frequency. Because of this capability, PLL circuits are useful in many applications such as frequency synthesizers, reference local oscillators, and particularly as stable reference clocks. PLL circuits have been applied in diverse circuits, such as circuits to eliminate noise that causes phase jitter in a signal.
In order to achieve lock, a PLL circuit can take an unpredictable and unspecific amount of time. Therefore, there is a need to know whether and when lock has occurred, or when it is safe to assume that the PLL has achieved lock. Knowledge about the locked condition can provide important information for more efficient system design. For example, in network systems that use a PLL circuit to generate the system clocks, a lock detection signal may be used to design the timing arrangement of other components in the network system. Lock indication also helps in the design of loop filters to reject noise and other interfering signals.
One technique for designing a lock detector circuit is described by the U.S. Pat. No. 6,320,469 entitled xe2x80x9cLock Detection for Phase-Locked Loopxe2x80x9d to Friedberg et al. (""469 patent). The ""469 patent discloses a method and lock detector for lock between a reference signal and a feedback signal of a phase-locked loop (PLL) circuit. The ""469 patent achieves lock detection by counting the number of cycles of both signals. If both signals are in a locked relation, the number of counts in an interval is the same. Otherwise, the number of complete cycles within an interval cannot be the same. There are two counters disclosed in the ""469 patent. One counter counts the number of clock cycles of the feedback signal and another counter counts the number of clock cycles of the reference signal in an interval. The feedback comparator determines whether the counted number of cycles is within an expected range. The qualification counter repeats the counting several times to make sure the same number of cycles has been achieved.
An object of the invention is to achieve a cost effective and reliable PLL""s lock detector circuit.
Another object of the present invention is to achieve a method of detecting the lock condition of a phase locked loop.
The above objects are achieved by means of a lock detection circuit for a phase locked loop (PLL) circuit. The lock detector circuit determines whether the PLL circuit is in lock condition in two stages. In the first stage, the lock detector circuit compares the phase of two clocks associated with the phase locked loop circuit, namely, a reference clock signal and a feedback clock signal to observe whether the phases of these two signals are in-phase or within a window of tolerance. The comparison of phases is established by a pair of cross-coupled flip-flop circuits having delayed inputs and outputs. In the second stage, the lock detector asserts the lock condition. The logic gate asserts whether the outputs to the flip-flop circuits are in lock condition after a certain number of counts have been established by a pair of counters. If the phases of the reference clock and the feedback clock are outside of the window of tolerance, a pair of counters is repeatedly reset and does not establish an output signal. However, if the phases of the two signals are in-phase or inside the window of tolerance, the counters are enabled and succeed in establishing an output signal. In other words, the counters count to full cycle and then go HIGH to assert that a locked relation has been achieved.